From: Bruno Haible Date: Tue, 9 Jan 2024 21:12:11 +0000 (+0100) Subject: jit/cache: Fix for hppa CPUs. X-Git-Tag: v1.0~533 X-Git-Url: https://gitweb.git.savannah.gnu.org/gitweb/?a=commitdiff_plain;h=0cb2e6ba787d548c2f62417e408992026e723a53;p=gnulib.git jit/cache: Fix for hppa CPUs. * lib/jit/cache.h (clear_cache): On hppa CPUs, use the 'fdc' and 'fic' instructions. --- diff --git a/ChangeLog b/ChangeLog index 7050708ce1..d327415df9 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,9 @@ 2024-01-09 Bruno Haible + jit/cache: Fix for hppa CPUs. + * lib/jit/cache.h (clear_cache): On hppa CPUs, use the 'fdc' and 'fic' + instructions. + jit/cache tests: Avoid test failure on OpenBSD. * tests/jit/test-cache.c (return1_code, return2_code): New constants. (main): On OpenBSD, use return1_code and return2_code instead of diff --git a/lib/jit/cache.h b/lib/jit/cache.h index 5bcc22cdc9..2a3469e0c4 100644 --- a/lib/jit/cache.h +++ b/lib/jit/cache.h @@ -99,6 +99,30 @@ clear_cache (void *start, void *end) addr += 8; } while (addr < end_addr); +#elif (defined __GNUC__ || defined __clang__) && defined __hppa + /* Use inline assembly. */ + /* The PA-RISC 1.1 Architecture and Instruction Set Reference Manual says: + "A cache line can be 16, 32, or 64 bytes in length." */ + /* XXX Is this good enough, or do we need the space register business + like in gcc/gcc/config/pa/pa.md and libffcall/trampoline/cache-hppa.c? */ + intptr_t cache_line_size = 16; + uintptr_t addr = (uintptr_t) start & ~cache_line_size; + uintptr_t end_addr = (uintptr_t) end; + do + { + asm volatile ("fdc 0(0,%0)" + "\n\t" "sync" + "\n\t" "fic 0(0,%0)" + "\n\t" "sync" : : "r" (addr)); + addr += cache_line_size; + } + while (addr < end_addr); + asm volatile ("nop" + "\n\t" "nop" + "\n\t" "nop" + "\n\t" "nop" + "\n\t" "nop" + "\n\t" "nop"); #elif (defined __GNUC__ || defined __clang__) && defined __m68k__ && defined __linux__ /* Use inline assembly to call the 'cacheflush' system call. sys_cacheflush (addr, scope, cache, len)