From: Bruno Haible Date: Sat, 28 Nov 2020 11:04:47 +0000 (+0100) Subject: asyncsafe-spin: Fix compilation error with GCC on 32-bit SPARC. X-Git-Tag: v1.0~3462 X-Git-Url: https://gitweb.git.savannah.gnu.org/gitweb/?a=commitdiff_plain;h=25a731a154380065d9fe92683c64d30f44bd3d6c;p=gnulib.git asyncsafe-spin: Fix compilation error with GCC on 32-bit SPARC. Reported by Paul Eggert in . * m4/sparcv8+.m4: New file. * modules/sparcv8+: New file. * modules/asyncsafe-spin (Depends-on): Add sparcv8+. --- diff --git a/ChangeLog b/ChangeLog index 55053793bc..fa21e9cd28 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,12 @@ +2020-11-28 Bruno Haible + + asyncsafe-spin: Fix compilation error with GCC on 32-bit SPARC. + Reported by Paul Eggert in + . + * m4/sparcv8+.m4: New file. + * modules/sparcv8+: New file. + * modules/asyncsafe-spin (Depends-on): Add sparcv8+. + 2020-11-28 Bruno Haible asyncsafe-spin: Fix build error with GCC on 32-bit SPARC. diff --git a/m4/sparcv8+.m4 b/m4/sparcv8+.m4 new file mode 100644 index 0000000000..2dbb8a90f4 --- /dev/null +++ b/m4/sparcv8+.m4 @@ -0,0 +1,42 @@ +# sparcv8+.m4 serial 1 +dnl Copyright (C) 2020 Free Software Foundation, Inc. +dnl This file is free software; the Free Software Foundation +dnl gives unlimited permission to copy and/or distribute it, +dnl with or without modifications, as long as this notice is preserved. + +dnl When compiling for SPARC in 32-bit mode, make sure that instructions for +dnl SPARC v8+ are accepted. This is necessary for multiprocessing (for +dnl instructions like 'membar' or 'cas'). All SPARC CPUs made since 1993 +dnl support this instruction set. But GCC in its default configuration, in +dnl 32-bit mode (64-bit mode assumes SPARC v9 or newer), still defaults to +dnl SPARC v7 instruction set: "By default (unless configured otherwise), GCC +dnl generates code for the V7 variant of the SPARC architecture." See +dnl +dnl + +AC_DEFUN([gl_SPARC_V8PLUS], +[ + AC_REQUIRE([AC_CANONICAL_HOST]) + + case "$host_cpu" in + sparc*) + if test -n "$GCC"; then + AC_CACHE_CHECK([whether SPARC v8+ instructions are supported], + [gl_cv_sparc_v8plus], + [AC_COMPILE_IFELSE( + [AC_LANG_PROGRAM( + [[]], + [[asm volatile ("membar 2");]])], + [gl_cv_sparc_v8plus=yes], + [gl_cv_sparc_v8plus=no]) + ]) + if test $gl_cv_sparc_v8plus = no; then + dnl Strangely enough, '-mv8plus' does not have the desired effect. + dnl But '-mcpu=v9' does. + CC="$CC -mcpu=v9" + CXX="$CXX -mcpu=v9" + fi + fi + ;; + esac +]) diff --git a/modules/asyncsafe-spin b/modules/asyncsafe-spin index fa27b087e1..fc734928db 100644 --- a/modules/asyncsafe-spin +++ b/modules/asyncsafe-spin @@ -10,6 +10,7 @@ signal-h stdbool sigprocmask windows-spin +sparcv8+ configure.ac: AC_REQUIRE([AC_C_INLINE]) diff --git a/modules/sparcv8+ b/modules/sparcv8+ new file mode 100644 index 0000000000..a4e38a8c4d --- /dev/null +++ b/modules/sparcv8+ @@ -0,0 +1,22 @@ +Description: +When compiling for SPARC, assume SPARC v8+ or newer. + +Files: +m4/sparcv8+.m4 + +Depends-on: + +configure.ac-early: +gl_SPARC_V8PLUS + +configure.ac: + +Makefile.am: + +Include: + +License: +LGPLv2+ + +Maintainer: +all