From: Bruno Haible Date: Tue, 9 Jan 2024 21:55:26 +0000 (+0100) Subject: jit/cache: Fix for ia64 CPUs. X-Git-Tag: v1.0~532 X-Git-Url: https://gitweb.git.savannah.gnu.org/gitweb/?a=commitdiff_plain;h=8e5cadc78b31bbf907df27be61368b39f36eb4bc;p=gnulib.git jit/cache: Fix for ia64 CPUs. * lib/jit/cache.h (clear_cache): On ia64 CPUs, use the 'fc', 'sync', 'srlz' instructions. --- diff --git a/ChangeLog b/ChangeLog index d327415df9..b62417964e 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2024-01-09 Bruno Haible + + jit/cache: Fix for ia64 CPUs. + * lib/jit/cache.h (clear_cache): On ia64 CPUs, use the 'fc', 'sync', + 'srlz' instructions. + 2024-01-09 Bruno Haible jit/cache: Fix for hppa CPUs. diff --git a/lib/jit/cache.h b/lib/jit/cache.h index 2a3469e0c4..f9da28125e 100644 --- a/lib/jit/cache.h +++ b/lib/jit/cache.h @@ -123,6 +123,26 @@ clear_cache (void *start, void *end) "\n\t" "nop" "\n\t" "nop" "\n\t" "nop"); +#elif (defined __GNUC__ || defined __clang__) && defined __ia64 + /* Use inline assembly. */ + /* The Intel IA-64 Architecture Software Developer's Manual volume 3 says: + "The line size affected is at least 32 bytes." */ + intptr_t cache_line_size = 32; + uintptr_t addr = (uintptr_t) start & ~cache_line_size; + uintptr_t end_addr = (uintptr_t) end; + do + { + /* Flush a cache line. */ + asm volatile ("fc %0" : : "r" (addr)); + addr += cache_line_size; + } + while (addr < end_addr); + /* Ensure the preceding 'fc' instructions become effective in the local + processor and all remote processors. */ + asm volatile ("sync.i"); + /* Ensure the preceding 'sync.i' instruction becomes effective in the + local processor's instruction cache. */ + asm volatile ("srlz.i"); #elif (defined __GNUC__ || defined __clang__) && defined __m68k__ && defined __linux__ /* Use inline assembly to call the 'cacheflush' system call. sys_cacheflush (addr, scope, cache, len)